EDN

Automatic test pattern generation with on-chip compression improves test quality

San Jose, Calif. — Magma Design Automation Inc. has launched the Talus automatic test pattern generation (ATPG) and Talus ATPG-X products with on-chip compression. These advanced ATPG products are ...
Electronic Design

Design for Test: ATPG keeps pace with design complexity

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.
Electronic Design

Test-Vector Generation Draws Major Gains

Through A Series Of Enhancements, This Tool Suite Raises The Performance Of Test-Pattern Generation And At-Speed Testing. To design complex ASICs in a timely and cost-effective manner, engineers must ...
Semiconductor Engineering

Reducing Chip Test Costs With AI-Based Pattern Optimization

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested.
Semiconductor Engineering

Supporting Multiple Time Domains In SoC Production Test

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for ...