Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

The reason I mention this here (in addition to the fact that I just like hearing myself say it) is that design engineers and verification engineers are like two sides of the same coin. Design ...

Chip designs are optimized for lower cost, better performance, or lower power. The same cannot be said about verification, where today very little effort is spent on reducing execution cost, run time, ...

This course covers the systematic design of real-time digital systems and verification techniques using field-programmable gate arrays (FPGAs). The course presents a top-down design methodology, where ...

A “shift-left” PCB design verification solution within the engineer’s authoring environment is the industry’s first of its kind, claims developer Mentor, a Siemens business. This new Xpedition ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...

Aparna Mohan pioneered a groundbreaking verification methodology for security-critical semiconductor designs that has transformed how the industry approaches security verification, yielding ...

Low power design techniques ” As designs are moving towards smaller and smaller technologies (90nm, 65nm ), leakage current has become significant and contributes to overall power. Designs are using ...

It is well known that the task of verification looms large in the design of digital IP, as well as the design of SoCs. The target is to reach 100% for both RTL code and functional coverage, minimizing ...