EDN

Get a hands-on tutorial in FPGA design at ESC Silicon Valley

I just heard from my chum Jason Pecor at Alorium Technology. Jason and his colleague, Bryan Craker, will be giving a 2-hour tutorial at ESC Silicon Valley 2016. Titled A Novel Hands-On Approach to ...
Hackaday

Learn FPGA With This Persistence Of Vision Hack

Everybody wants to give FPGA development a try and here’s a great way to get into it. You can build your own Persistence of Vision display using a $30 dev board. It’s a fun project, and you’ll learn ...
EDN

Tutorial: Designing an FPGA from scratch – It’s like déjà vu all over again!

Where does the time go? About four years ago as I pen these words, I was introduced to expert Swedish ASIC designer Sven-Åke Andersson. At that time, Sven was aware that, with their increasing NRE ...
The Droid Guy

Hands On With Mars FPGA A Powerhouse Development Board Tutorial

The MARS FPGA is an ambitious, open-source project designed to surpass the capabilities of existing FPGA-based retro gaming systems, particularly the MiSTer FPGA. This powerhouse development board ...
Business Wire

DVCon Europe “Must See”: Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...
Design-Reuse

A tutorial on tools, techniques, and methodology to improve FPGA designer productivity

What is the biggest factor affecting the productivity of FPGA design cycles? Many designers say achieving timing closure is critical in getting a design to market – and with good reason. Achieving ...
Electronics Weekly

Arm adds fpga option and new business model to DesignStart

Xilinx Developer Forum, California: Arm Cortex-M1 and Cortex-M3 cores have been added to the DesignStart portfolio in a collaboration with Xilinx to bring instant and license-free access to developers ...
Semiconductor Engineering

Automated Conversion Of Xilinx Vivado Projects To ALINT-PRO

Aldec’s ALINT-PRO design verification solution performs static RTL and design constraints code analysis to uncover critical design issues early in the design cycle. The product helps FPGA developers ...
Electronics Weekly

Xilinx adds machine learning optimisation to Vivado to accelerate design cycle

Claiming to be able to reduce design compile times by a factor of five, Xilinx has launched the Vivado ML Editions tool suite. The latest addition to the company’s Vivado tool suite is believed to be ...