EDN

Calypto CTO to Present Low-Power Tutorial During VLSI Conference in India

Calypto™ Design Systems Inc., the leader in sequential analysis technology, announced today that Anmol Mathur, Calypto’s chief technology officer, will present a tutorial on system-on-chip (SoC) power ...
TechRepublic

Low Power VLSI CMOS Design by DCG Technique

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown ...
EDN

Low power implementation techniques for ASIC physical design

In the semiconductor domain, the operating frequency of devices and the number of transistors in a single module increase over time. In this article, we will look at widely known low power ...
mccormick.northwestern.edu

VLSI Lab Wins ISLPED Design Contest Award

Professor Jie Gu and members of his Very Large-Scale Integration Lab team won the Design Contest Award at the premier ACM/IEEE International Symposium on Low Power Electronics and Design Northwestern ...
mccormick.northwestern.edu

Sustainable Energy and Low-Power Design

Achieving sustainability occurs by reducing the amount of energy consumed during manufacturing and throughout the lifetime of a device. Semiconductors play a key role in sustainable energy by enabling ...
Semiconductor Engineering

Low-Power IC Design Without Compromise

In the process of creating ICs, the digital implementation stage is focused on meeting the performance, power, and area (PPA) targets defined for the design. Traditionally, when talking about PPA ...
Electronic Design

Solving Six Low-Power Debug Pitfalls

Simulation-based debug challenges arise when verifying the behavior of a power-managed SoC from the front-end design phase through the back-end implementation phase. We'd also like to recognize the ...
Semiconductor Engineering

Simplifying Ultra-Low Power System Design

With any low-power design, the designer has the choice between choosing low-power components or switching off the power to peripheral devices. When considering the choice of non-volatile flash ...
Electronic Design

Designing Ultra-Low-Power Sensor Nodes for IoT Applications

In many Internet of Things (IoT) applications, minimizing power consumption is a key design requirement. IoT capability involves adding sensors and connectivity to a valve or similar device in a ...
Nature

Low Power SRAM Design and Technology

Low power Static Random-Access Memory (SRAM) design remains at the forefront of research in modern electronics due to its critical role in minimising energy consumption while maintaining high ...
TechRepublic

Low Power State Retention Technique for CMOS VLSI Design

Mobile computing and mobile communication applications which are powered by battery, the battery life is a major concern. Leakage power dissipation is critical in VLSI circuits as the battery leaks ...