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IEEE7h
A 10-bit high speed pipelined ADC - IEEE Xplore
The design of a 10-bit, 200MS/s Pipelined Analog to Digital Converter (ADC) is presented in this paper. The implemented pipelined ADC employs techniques such as pipeline stage scaling algorithm, to ...
IEEE2d
A 1.2GS/s 11b Time-Interleaved SAR ADC with Low-Cost Derivative-Based Background Timing-Skew Calibration and Variable-Load Comparators - IEEE Xplore
It outperforms the conventional design in both speed and energy efficiency. Equipped with the proposed calibration technique and comparators, a prototype 1.2GS/s 11b TI SAR ADC with an on-chip ...