IEEE

Designing of AES-128 Encryption Algorithm Using System Verilog VLSI

Abstract: This paper details a comprehensive study on the implementation of the Advanced Encryption Standard (AES) using Very Large Scale Integration (VLSI) technology for the purpose of creating ...
IEEE

FPGA Implementation of High-Speed Accelerators for CNN Architecture Using 3D Systolic Array Architecture

Abstract: Convolution Neural Networks (CNNs) are pivotal in image processing. Prominent CNN models include SqueezeNet, MobileNet, Xception, VGG-16, and AlexNet. These models transform 2D data to 1D, ...