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*A sequential circuit is shown in Figure 4-49. The timing parameters for the gates and flip-flops are as follows: Inverter: tpd=0.01  ns XOR gate: tpd=0.04  ns Flip-flop: tpd=0.08  ns, ts=0.02  ns , and th=0.01  ns (a) Find the longest path delay from an external circuit input passing through gates only to an external circuit output. (b) Find the longest path delay in the circuit irom an external input to positive clock edge. (c) Find the longest path delay from positive c
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