Direct Mapping with Example: Cache Mapping Video Lecture | Crash Course: Computer Science Engineering (CSE)

SOLVED:For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. What is the cache block size (in words)? How many entries does the cache have? What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180

SOLVED: Consider now a fully associative cache where each cache line holds 16 machine words (i.e., the basic addressable unit). The machine word size is 4 bytes. The cache can store 32 Kbytes of data, and the main memory can store 2 Mbytes of data.How many bits of a memory address should be used for the tag?Write your answer in a Base 10 number (and only write down the number).

Answered: A main memory has 1 giga-words of byte addressable memory, with four bytes per word. The memory system uses a direct mapped cache. There are 4K cache lines, and… | bartleby

GATE AIMERS 2022 | CS | Computer Organization | Cache Mapping Techniques | Satya Narayana