Write the Verilog HDL design for the Mealy FSM and Moore FSM of a sequence detector with one input X and one output Z. The detector should recognize the input sequence "001" or "110". The detector should keep checking for the appropriate sequence and should not reset to the initial state after it has recognized the sequence. The detector initializes to a reset state when input, RESET is activated. Verify your design using a testbench.
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